1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a method and apparatus for reducing leakage current in circuits implemented using complementary metal oxide silicon (CMOS) transistors.
2. Related Art
Complementary metal oxide silicon (CMOS) transistors are often used to implement integrated circuits as is well known in the relevant arts. One problem with typical CMOS transistors is that a small amount of current may flow through the transistors from a power source even when the transistors are in an off state. Such flow is often referred to as leakage, the corresponding current is referred to as leakage current. In several environments (e.g., in portable applications), it is generally desirable to reduce the leakage current, for example, to minimize overall power consumption.
Various approaches are known in the prior art to reduce leakage current. In one approach, the leakage current is reduced by increasing a threshold voltage (Vt) of a CMOS transistor. As is well known, Vt represents a minimum voltage level, applied between a gate terminal and a source terminal of the transistor, below which the drain-to-source current substantially equals zero.
One problem with such an approach is that the switching speed of transistors having high threshold voltage, is generally low, thereby leading to integrated circuits with low throughput performance (measure of how quickly an output signal is generated in response to corresponding input signal). Accordingly, such an approach may be undesirable in several environments.
Accordingly, in one alternative approach, cells containing CMOS transistors (often) all of low Vt (“low Vt transistors”) are used on critical paths and cells containing CMOS transistors all of high Vt (“high Vt transistors”) are used elsewhere in CMOS circuits. As a critical path refers to a path offering a long(est) delay, the use of low Vt transistors reduces the delay in the critical path, thereby potentially increasing the throughput performance of the circuit. In addition, the leakage current is reduced due to the use of high Vt transistors elsewhere in the circuit.
When a cell designed with all high Vt transistors is included in a path to reduce leakage, the resulting higher delay (caused by the cell) may cause other paths containing the cell to become critical paths (which violate the timing requirements at a desired high speed of operation of an integrated circuit). Such a situation may require cells in these other paths to be designed with low Vt transistors, which again increases the aggregate leakage current in the entire integrated circuit.
In another approach, a high Vt transistor may be introduced in a path connecting a CMOS transistor to the power supply. When the circuit is in a non-operational mode (e.g., standby or sleep mode), the high Vt transistors are switched off which causes the transistors to be disconnected from power supply. Thus, the leakage current may be reduced at least in such non-operational modes. One problem with such an approach is the requirement of more high Vt transistors and the resulting potential problem with additional space and/or routing requirements.
What is therefore needed is a method and apparatus for reducing leakage current in circuits implemented using CMOS transistors while addressing one or more of the problems noted above.